(a) Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of forming shallow trench isolation (STI) in a semiconductor device.
(b) Description of the Related Art
Recently, as a metal-oxide-semiconductor (MOS) transistor has become highly integrated, a conventional local oxidation of silicon (LOCOS) process has been replaced with a shallow trench isolation (STI) process.
In a typical STI process, a trench is formed by etching a silicon substrate using a silicon nitride pattern formed on the silicon substrate. Subsequently, an insulation layer is formed on the trench and the silicon nitride pattern, which is then planarized by a chemical mechanical polishing (CMP) process so as to expose the silicon nitride pattern. Finally, the silicon nitride pattern is removed to expose the silicon substrate, so that a field insulation layer, that is an STI layer, is formed.
However, in such an STI layer, a line width thereof depends on a design rule of the photolithography and etching processes, and so an STI layer having a smaller line width than the design rule cannot be formed.
The above information disclosed in this Background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form part of the prior art with respect to the present invention.